IEEE VLSI TITLES 2016-2017 STARTING AT 1500 RS
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Sl.No
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PROJECT CAPTION
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YEAR
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IXVI1
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2016-2017
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IXVI2
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2016-2017
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IXVI3
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Improving
Convergence and Simulation Time of Quantum Hydrodynamic Simulation:
Application to Extraction of Best 10-nm Fin FET Parameter Values
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2016-2017
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IXVI4
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A Fine-Grained
Control Flow Integrity Approach Against Runtime Memory Attacks for Embedded
Systems
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2016-2017
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IXVI5
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Analysis and
Mapping for Thermal and Energy Efficiency of 3-D Video Processing on 3- D
Multicore Processors
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2016-2017
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IXVI6
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Design
Methodology for Voltage-Scaled Clock Distribution Networks
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2016-2017
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IXVI7
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A VHDL
Implementation of UART design with BIST capability
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2016-2017
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IXVI8
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A Low-Voltage Radiation-Hardened
13T SRAM Bitcell for Ultralow Power Space Applications
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2016-2017
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IXVI9
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Utilization-Aware
Self-Tuning Design for TLC Flash Storage Devices
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2016-2017
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IXVI10
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Fault
Tolerant Parallel Filters Based on Error Correction Codes
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2016-2017
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IXVI11
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5-bit
5-GS/s Noninterleaved Time-Based ADC in 65-nm CMOS for Radio-Astronomy
Applications M
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2016-2017
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IXVI12
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Wearout Resilience in NoCs Through an Aging Aware Adaptive
Routing Algorithm
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2016-2017
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IXVI13
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Optimum
pMOS-to-nMOS Width Ratio for Efficient Subthreshold CMOS Circuits
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2016-2017
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IXVI14
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Level-Converting
Retention Flip-Flop for Reducing Standby Power in ZigBeeSoCs
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2016-2017
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IXVI15
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A
Compact One-Pin Mode Transition Circuit for Clock Synchronization in
CurrentMode- Controlled Switching Regulators
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2016-2017
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IXVI16
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Low-Cost
On-Chip Clock Jitter Measurement Scheme
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2016-2017
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IXVI17
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Diagnosis
and Layout Aware (DLA) Scan Chain Stitching
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2016-2017
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IXVI18
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0. Enhanced
Built-In Self-Repair Techniques for Improving Fabrication Yield and
Reliability of Embedded Memories
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2016-2017
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IXVI19
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A
Low-Latency and Low-Power Hybrid Scheme for On-Chip Networks
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2016-2017
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IXVI20
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Accelerated
Accurate Timing Yield Estimation Based on Control Variates and Importance Sampling
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2016-2017
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IXVI21
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A
Calibration Technique for Bang-Bang ADPLLs Using Jitter Distribution
Monitoring
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2016-2017
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IXVI22
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Design
of Efficient Content Addressable Memories in High-Performance FinFET
Technology
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2016-2017
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IXVI23
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Characterization
of the Proximity Effect from Tungsten TSVs on 130-nm CMOS Devices in 3-D ICs
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2016-2017
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IXVI24
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Area–Delay–Power
Efficient Carry-Select Adder
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2016-2017
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IXVI25
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Area-Delay-Power Efficient Fixed-Point LMS Adaptive Filter
With Low Adaptation-Delay
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2016-2017
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IXVI26
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Constructions of Memoryless Crosstalk Avoidance
Codes via C-Transform
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2016-2017
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IXVI27
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Dynamic Thermal Estimation Methodology for High
Performance 3-D MPSoC
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2016-2017
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IXVI28
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The Impact of Aging on a Physical Unclonable
Function
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2016-2017
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IXVI29
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Partial Access Mode: New Method for Reducing Power
Consumption of Dynamic Random Access Memory
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2016-2017
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IXVI30
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VLSI Design of a Large-Number Multiplier for Fully
Homomorphic Encryption
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2016-2017
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IXVI31
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An Offset-Canceling Triple-Stage Sensing Circuit for
Deep Submicrometer STT-RAM
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2016-2017
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IXVI32
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Critical-path analysis and low-complexity
implementation of the LMS Adaptive algorithm
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2016-2017
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IXVI33
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A 28-nm CMOS 1 V 3.5 GS/s 6-bit DAC With
Signal-Independent Delta-I Noise DfT Scheme
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2016-2017
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IXVI34
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An 8 bit 0.3–0.8 V 0.2–40 MS/s 2-bit/Step
SAR ADC With Successively Activated Threshold Configuring Comparators in 40
nm CMOS
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2016-2017
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IXVI35
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Design of Self-Timed Reconfigurable
Controllers for Parallel Synchronization via Wagging
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2016-2017
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IXVI36
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Design Techniques to Improve Blocker
Tolerance of Continuous-Time __ ADCs
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2016-2017
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IXVI37
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Z-TCAM: An SRAM-based Architecture for TCAM
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2016-2017
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IXVI38
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Quaternary Logic Lookup Table in Standard
CMOS
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2016-2017
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IXVI39
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A Low-Jitter Cell-Based Digitally Controlled
Oscillator With Differential Multiphase Outputs
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2016-2017
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IXVI40
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Asynchronous Domino Logic Pipeline Design
Based on Constructed Critical Data Path
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2016-2017
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IXVI41
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A
Low-Latency and Low-Power Hybrid Scheme for On-Chip Networks
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2016-2017
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IXVI42
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A Low-Cost Low-Power All-Digital
Spread-Spectrum Clock Generator
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2016-2017
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IXVI43
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All Digital Energy Sensing for Minimum
Energy Tracking
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2016-2017
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IXVI44
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Built-in Self-Calibration and Digital-Trim
Technique for 14-Bit SAR ADCs Achieving ±1 LSB INL
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2016-2017
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IXVI45
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A CMOS PWM Transceiver Using
Self-Referenced Edge Detection
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2016-2017
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IXVI46
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Obfuscating DSP Circuits via High-Leve5 Transformations
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2016-2017
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IXVI47
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Revisiting Central Limit Theorem: Accurate
Gaussian Random Number Generation in VLSI
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2016-2017
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IXVI48
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Watermarking in Hard Intellectual Property
for Pre-Fab and Post-Fab Verification
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2016-2017
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IXVI49
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A 0.25-V 28-nW 58-dB Dynamic Range
Asynchronous Delta Sigma Modulator in 130-nm Digital CMOS Process
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2016-2017
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IXVI50
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Power and Bandwidth Scalable 10-b 30-MS/s
SAR ADC
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2016-2017
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VLSI (very large-scale
integration) is the current level of computer microchip miniaturization and
refers to microchips containing in the thousands of ten thousands of transistors.
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Relationship between embedded system
and VLSI:
It uses
the chip developed by VLSI technology, to produce efficient systems. That
is, technology behind the embedded system is VLSI
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CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits. CMOS technology is also used
for several analog circuits such as image sensors (CMOS sensor), data converters, and highly integrated transceivers for many types of communication.
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IEEE VLSI TITLES 2016-2017
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ASIC: An application-specific
integrated circuit (ASIC) is an integrated circuit designed for a
particular use, rather than intended for general-purpose use. Processors,
RAM, ROM, etc are examples of ASICs.
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